Field of the Invention
The present invention relates to a method of manufacturing an imaging apparatus.
Description of the Related Art
In Japanese Patent Application Laid-Open No. 2008-098373, there is disclosed a technology for an imaging apparatus, aimed at reducing a global step height of an interlayer insulating layer, which is a height difference on a surface of the interlayer insulating layer in an entire chip region.
The imaging apparatus disclosed in Japanese Patent Application Laid-Open No. 2008-098373 includes a pixel region in which a plurality of pixels are arranged, a peripheral circuit region arranged on the periphery of the pixel region, and a scribe-lane region that is a chip peripheral portion. An interlayer insulating layer is formed in each of the regions. The interlayer insulating layer thus formed in each of the regions is planarized by chemical mechanical polishing (CMP).
In the pixel region, protective films for protecting photodiodes are formed, and pattern density of gate electrodes is high. The interlayer insulating layer is formed so as to cover the protective films and the gate electrodes, and hence an average height of the surface of the interlayer insulating layer in the pixel region immediately after film formation is higher than that in the peripheral circuit region. Specifically, the area of the pixel region to be polished in a CMP step is larger than that of the peripheral circuit region, and hence the polishing rate has a gradient over the entire chip. Thus, the surface of the interlayer insulating layer after the CMP step may have a global step height.
In order to reduce the global step height that may be generated in this manner, in the imaging apparatus disclosed in Japanese Patent Application Laid-Open No. 2008-098373, a dummy pattern is formed in each of the peripheral circuit region and the scribe-lane region. Accordingly, an average height of the surface of the interlayer insulating layer in the peripheral circuit region and the scribe-lane region before the CMP step is made closer to an average height of the surface of the interlayer insulating layer in the pixel region, with the result that the global step height is reduced.
In the configuration disclosed in Japanese Patent Application Laid-Open No. 2008-098373, a circuit for scanning the pixels, a circuit for processing signals, and the like are formed in the peripheral circuit region. The dummy pattern needs to be arranged so as not to affect the characteristics of the circuits as much as possible, and hence the peripheral circuit region has a limited area in which the dummy pattern can be formed. Thus, the amount of reducing the difference in average height before planarization may be insufficient when the method involving forming the dummy pattern is employed alone.